Recently, ultra high density storage devices have been proposed using a three-dimensional (3D) stacked memory structure sometimes referred to as a Bit Cost Scalable (BiCS) architecture. For example, a 3D NAND stacked memory device can be formed from an array of alternating conductive and dielectric layers. A memory opening is formed through the layers to define many memory layers simultaneously. A NAND string is then formed by filling the memory opening with appropriate materials. A straight NAND string extends in one memory opening, while a pipe- or U-shaped NAND string (p-BiCS) includes a pair of vertical columns of memory cells. Control gates of the memory cells may be provided by the conductive layers.
In conventional 3D NAND strings, a semiconductor channel including a stack of two amorphous silicon layers is employed. A first amorphous silicon layer is employed to cover sidewalls of a tunneling dielectric layer, and the second amorphous silicon layer is employed to provide electrical contact to an underlying semiconductor material. The overall thickness of the semiconductor channel is in a range from 15 nm to 20 nm. The use of two layers for the semiconductor channel leads to formation of a defective interface between the first and second amorphous silicon layers. The defective interface provides a high trap density, which degrade charge carrier mobility and cell current. High level of defects and grain boundaries may remain in the stack of two silicon layers that is obtained by annealing the stack of amorphous layers. Such defects and grain boundaries are detrimental to various performance metrics including the sub-threshold slope and the boosting potential.